Phase-lock systems for variably moving one signal in frequency/phase until it matches or "locks" with another reference signal are well known. Likewise, voltage controlled oscillators as an element in such systems are also well known in the art.
As a general rule voltage controlled oscillators are confined to a narrow frequency range, and the controllable frequency variations are also within a narrow frequency band about a center, or reference frequency. The reference frequency is determined by the given oscillator's design configuration.
As semi-conductor and "chip" technology has spread, the design criteria for many circuits, including voltage controlled oscillators, has become increasingly rigorous. For example, current chip technology demands low power consumption, i.e. low operating voltages, and high noise immunity over increasingly expanding frequency ranges. Today's technology also seeks linearity over a broadband frequency range. These operational requirements eliminate many of the conventional prior art approaches.
Typical examples of two major candidates for conventional oscillator design approaches are set forth in two related articles entitled Design of PLL-Based Clock Circuits, by Deog-Kyoon Jeong et al published in the IEEE Journal of Solid State Circuits, Vol. sc-22, No. 2, April 1987, pages 255 through 261 and A Variable Delay Line PLL for CPU-Co-processor Synchronization by Mark Johnson and Edwin Hudson, published in the IEEE Journal of Solid State Circuits on Oct. 18, 1988 at pages 1218 through 1223. These articles describe two different oscillator techniques.
In one technique a control voltage is applied to a series-connected element that "current starves" an inverter. In the second approach, employing a bipolar multi-vibrator, the control voltage in essence varies a load capacitance. FIG. 3a at page 1219 of the Johnson and Hudson article depicts a CMOS current starved oscillator design, while FIG. 3b of that same article depicts a shunt capacitor delay stage.
Several cells in the Johnson article were cascaded together to afford a desired amount of delay adjustment range as shown, for example, in FIG. 5, of that paper. Of considerable interest is the fact that the designers elected to go with the shunt capacitor delay cell for a cascade circuit approach. Apparently a major factor in their design consideration was the severe non-linearity of the current starved approach.
In FIG. 4 of the Johnson article, delay time as a function of control voltage is shown for both the current-starved and shunt-capacitor techniques. The current starved inverter's delay propagation, as the control voltage moves toward zero, goes asymptotically toward infinity. A single stage, or cell, shows a frequency range of about 17 Mega Hertz (MHz) with a gain of about 12 MHz per volt. If a design criteria specifies linearity and a 3 volt operating range, the best case gain is about 180 MHz/3 volts or about 60 MHz per volt.
However, as shown in FIG. 4 of the reference, the circuit's characteristic is extremely non-linear and has high gain regions. Such high gain brings about numerous drawbacks including low noise immunity. In addition, the steep slope of the delay characteristic shown for the lower-voltage operational range of the current starved approach, generally indicates a noisier circuit operation. Thus, an unstable high gain region is present in the circuit approach of FIG. 3a, which tends to unduly multiply spurious noise signals. A spurious noise signal, for example, on a control lead would be multiplied many times by the circuit's high gain. For these reasons the classic current starved technique is often rejected for consideration in oscillator design.
In spite of the above-noted deficiencies of conventional current starved inverter approaches, however, the inventor has persisted and has invented a broadband, low power, and highly noise free voltage controlled oscillator circuit based upon a current starved inverter cell. In the novel approach of the invention, the troublesome high gain area is eliminated by an anti-high-gain circuit. The result is a highly improved low gain current starved inverter cell. Moreover, by combining a series of the improved low gain cells in a variable length, variable delay ring oscillator, a broadband frequency range is provided which was not heretofore thought possible in the art.